PKTI=Val_0x0, FIFOBUSY=Val_0x0, BYTEEN=Val_0x0, STSI=Val_0x0, PKTSTATE=Val_0x0
FIFO Debug Status Register
| FIFOBUSY | FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: All other fields of this register All fields of the ETH_MTL_FIFO_DEBUG_DATA register 0 (Val_0x0): FIFO busy not detected 1 (Val_0x1): FIFO busy detected |
| PKTSTATE | Encoded Packet State This field is used to get the control or status information of the selected FIFO. Tx FIFO: 0 (Val_0x0): Packet data 1 (Val_0x1): Control word/normal status 2 (Val_0x2): SOP data/last status 3 (Val_0x3): EOP data/EOP |
| BYTEEN | Byte Enables This field indicates the number of data bytes valid in the data register during Read operation. This is valid only when PKTSTATE is 0x2 (EOP) and Tx FIFO or Rx FIFO is selected. 0 (Val_0x0): Byte 0 valid 1 (Val_0x1): Byte 0 and Byte 1 are valid 2 (Val_0x2): Byte 0, Byte 1, and Byte 2 are valid 3 (Val_0x3): All four bytes are valid |
| PKTI | Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO. This bit is reset when 1 is written to this bit. 0 (Val_0x0): Receive packet available interrupt status not detected 1 (Val_0x1): Receive packet available interrupt status detected |
| STSI | Transmit Status Available Interrupt Status When set, this bit indicates that the Slave mode Tx packet is transmitted, and the status is available in Tx Status FIFO. This bit is reset when 1 is written to this bit. 0 (Val_0x0): Transmit status available interrupt status not detected 1 (Val_0x1): Transmit status available interrupt status detected |
| LOCR | Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO. Debug Access Mode: This field contains the Write or Read pointer value of the selected FIFO during Write or Read operation, respectively. |